COST-OPTIMISED / ENTRY-LEVEL

5G NR LDPC encoder and decoder

Run-time code selection for a compact encoder and a throughput-bounded decoder. Review the exact configuration before integration.

IN DEVELOPMENT Candidate products. Package release is pending; price and licence are by quote.

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Where these cores fit

Both base graphs and lifting sizes are selected per block. The diagram shows an application context, not a complete NR PHY or a deployed system.

Conceptual integration: encoding, external channel processing, decoding.
Conceptual integration: encoding, external channel processing, decoding.

Entry-level encoder

P=64, run-time base graph, lifting size and parity-row selection; maximum Z=384. The folded encoder trades peak throughput for fewer resources.

ProbeClockLUTFFBRAM36-eq / DSP
Runtime P64 / ZMAX384374.8 MHz MEASURED1,709 MEASURED612 MEASURED3 / 0 MEASURED

Routed out-of-context probe, xczu67dr-fsve1156-2-i, Vivado 2025.2. Product probe remains unsettled; this is not a guaranteed integration clock.

AlgoSilicon encoder resources from the routed probe.
AlgoSilicon encoder resources from the routed probe.

The reference model agrees with MATLAB nrLDPCEncode: zero errors in 1,507,528 compared bits across 54 cases. This is model cross-validation, with separate RTL conformance evidence; it is not a board result. MEASURED

Interface: ready/valid words with marked headers and P-lane payloads. For a lifting size not divisible by 64, the active lane count is a divisor of Z; partial final words do not match the MathWorks block interface. AXI integration and rate matching require separately agreed scope.

Request encoder scope and price

Entry-level decoder

Layered normalised min-sum, six-bit LLRs. Choose a P=64 or P=128 build; code mode, lifting size and one to eight iterations are selected per block (MAX_ITER=8).

ProbeClockLUTFFBRAM36-eq / DSP
P64 / ZMAX384154.8 MHz MEASURED35,319 MEASURED6,514 MEASURED124 / 0 MEASURED
P128 / ZMAX384163.3 MHz MEASURED60,244 MEASURED12,552 MEASURED124 / 0 MEASURED

Both are unsettled routed experiments on xczu67dr-fsve1156-2-i, Vivado 2025.2. Timing searches did not converge: these are closed trial periods, not maximum or guaranteed operating frequencies. Throughput estimates remain withheld pending reconciliation with the routed results.

AlgoSilicon P64 decoder resources from the routed probe.
AlgoSilicon P64 decoder resources from the routed probe.

The model passes statistical comparison against nrLDPCDecode and the Wireless HDL NR LDPC Decoder reference over 7,000 pinned channel frames, under a 95% interval criterion. The golden-vector leg has 22 model bit errors versus 267 reference errors in 38,086 compared bits. These are scoped software comparisons; they do not demonstrate zero BER or board performance. MEASURED

Discuss P64 · Discuss P128

Evaluation and delivery

Source licensing, encrypted timed evaluation, device/configuration-specific netlists and offline trials are requested delivery forms. No tier is currently accepted for release; admission and applicable configuration, timing, simulation and package checks remain required. Plaintext timed evaluation is internal staging and is not a customer protection offer. No implementation download or automatic checkout is enabled here.

The existing hosted lab demonstrates a different NR decoder implementation. Use it to explore channel and code settings; its results do not validate these P64/P128 products. No board deployment, Vivado block-design capture or dedicated hosted trial is claimed for this candidate line.

Explore the existing NR lab

Earlier source-tier runs recorded passing simulator conformance, customer-vector playback, independent MATLAB reference and documentation checks for the runtime P64 encoder and P64/P128 decoders. Recorded decoder cross-validation includes the pinned 7,000-frame statistical comparison. Current implementation-quality checks require further alignment. Candidate admission, fresh qualification and protected-tier validation remain pending. All packages stay in internal staging; exact availability is confirmed before invoicing or delivery.

P64 decoder encrypted-evaluation and netlist archives were staged internally in the earlier run and need fresh validation. P128 source packaging has recorded simulation/reference checks; current qualification, protected packages and the decoder timed-netlist trial remain pending. These artifacts are not downloadable customer releases.