IP CORE · 3GPP LTE CHANNEL DECODING

LTE Turbo Decoder

A synthesizable Max-Log-MAP decoder candidate for the LTE Turbo code, covering all 188 QPP block sizes from K=40 to K=6144. The current six-iteration, 5-bit-input build is routed on Zynq UltraScale+ RFSoC and checked on the board with an independent expected stream and a deliberately corrupted control.

Request datasheet & evaluation
MEASURED POINT

One configuration, with its boundaries attached

Device xczu67dr-fsve1156-2-i, Vivado 2025.2, out-of-context post-route implementation; K=6144, six iterations, WINDOW=32, 5-bit channel input.

450.045 MHz
Post-route clock, setup and hold met MEASURED
31.539 Mb/s
Frame throughput from 87,673 clocks MEASURED
2,657 LUT
1,177 FF / 6.5 BRAM / 0 DSP MEASURED
0 mismatches
3,003,668,343 checked board cycles at 299.917 MHz MEASURED
ARCHITECTURE

Spend time to avoid duplicating the largest engine

The current candidate time-reuses one Max-Log-MAP SISO engine through twelve half-iterations. Natural and QPP order are explicit, and extrinsic information returns with frame and phase identity attached. This keeps the architecture reviewable while supporting every legal LTE QPP block size.

Simplified LTE Turbo decoder architecture decision
Conceptual architecture decision. It explains ownership and reuse; it is not an RTL schematic.

Scope boundary. This decoder core does not claim CRC, rate matching, HARQ, code-block segmentation, or a complete LTE baseband. Those functions can be integrated as a defined system engagement.

TRADE-OFF

A same-flow comparison that preserves the loss

The comparison uses the same device, block length, iteration count, input precision and implementation flow. It is a Pareto comparison, not a single-number victory claim.

LTE Turbo decoder candidate and MathWorks baseline trade-off
Post-route comparison on xczu67dr-fsve1156-2-i. The MathWorks throughput value is an upper bound.
Post-route resultAlgoSilicon candidateMathWorks R2026a baseline
Clock450.045 MHz MEASURED396.354 MHz MEASURED
Logic2,657 LUT / 1,177 FF MEASURED3,446 LUT / 4,677 FF MEASURED
Memory / arithmetic6.5 BRAM / 0 DSP MEASURED7.0 BRAM / 0 DSP MEASURED
First-decision latency75,379 cycles MEASURED74,695 cycles MEASURED
Frame throughput31.539 Mb/s MEASURED≤28.0 Mb/s MEASURED UPPER BOUND

The candidate uses 789 fewer LUTs, 3,500 fewer flip-flops and 0.5 fewer BRAMs, while closing 53.691 MHz higher. It reaches its first decision 684 cycles later. The baseline did not record the next-frame acceptance boundary, so its throughput is deliberately reported only as an upper bound. Neither point dominates the other.

ASSURANCE

The board pass has a control that must fail

Verification crosses independent models, RTL runs, routed implementation, and board playback. The RTL conformance record covers 153 complete runs over nine operating points. The board stream covers five legal frame sizes from K=40 through K=6144, with 8,883 input words and 8,848 output decisions.

The current board record passed for 3,003,668,343 cycles with zero mismatches at 299.917 MHz. A deliberately mutated RTL build produced 56,770,955 mismatches and failed, showing that the checker can turn red.

LTE Turbo decoder current board evidence record
Selected fields from the current machine-readable board record.
Evaluate the core against your acceptance boundary

We can package the candidate for your device, interfaces, throughput target and verification workload. Measured results remain tied to the configuration and flow that produced them.

Request an evaluation

Read the engineering case study: from task to board-tested RTL in two days.