How we design, generate, and prove verified FPGA IP, written for the engineers who evaluate it. Every number in these pieces is a measured result.
A CCSDS AR4JA LDPC decoder matched its golden model bit for bit in simulation across all nine code points, then lost the head of every frame after the first on real hardware. The cause was not in the decoder, and the vendor manual named it faster than a waveform would have.
A second FPGA on the board used to need a service cable for every firmware change. The update now runs over the 10-gigabit link the two chips already share: the image is written into the configuration flash beside the target and read back byte by byte, then one in-band command reboots the chip into it. Proving which copy it booted took a counter, not a flag.
Two large FPGAs on one board over eight 10-gigabit lanes. Neither chip alone had the room, so the second became an extension of the first: a compute node and four gigabytes of remote memory, each verified byte-exact on real silicon. Bringing up the link meant catching a reversed wiring record that every simulation had faithfully obeyed.
High-value radio and FPGA hardware sits idle because crossing from an algorithm to a working system is still done by hand. What we are building to change that, and how bit-exact validation makes AI-generated hardware trustworthy.
A reference transceiver written for a vendor evaluation board, moved onto custom hardware over a cable loopback. Two failures passed every simulation and only showed up on silicon: a defect the build itself introduced, and one converter configuration field.
A partner trial board arrived with no operating system on it. An AI drove the whole bring-up, proving each layer of hardware before building the next, then built and installed Linux and booted it to a login prompt reachable over ssh.
A first-principles re-build of IBM's Relay-BP decoder for the gross quantum code, generated from a model proven bit-exact at every layer. It lands on the published silicon envelope, and the genuine headroom is algorithmic: stop early when a decode stalls, which cuts worst-case latency without costing accuracy.
A generated decoder, handed to an AI to shrink its FPGA footprint. AI folded the logic to a third, diagnosed that the lost clock was a micro-architecture problem not a folding one, swapped in a rotating read to recover 160 MHz, backed out of a measured dead end, and proved every change bit-exact.
A complete 802.11a receiver went from a MATLAB reference design to bit-exact FPGA hardware no one wrote by hand, and recovered a MATLAB-generated waveform with zero bit errors. How every layer was checked against the standard.
A 5G NR cell-search receiver went from a reference design to FPGA hardware no one wrote by hand, and read three real over-the-air cells to a consistent broadcast message. The detector is 38% smaller than an earlier HLS implementation.
A 5G LDPC decoder, generated as RTL from a Python algorithm, optimized from 221 to 463 MHz, past a paid commercial IP on the same FPGA. The hard part was the data dependency between layers, not where to add a register.
One parameterized flow generates, timing-closes, and bit-exact verifies twenty 5G LDPC decoder configurations. Tuning one design is a special case; automating the whole batch, and proving every one, is a method.