LDPC Decoders

Our flagship configuration (base graph 2, lifting size 384, K = 3840) was placed and routed on the same AMD Kintex UltraScale+ device class the commercial reference IP publishes its numbers on. All figures below are from Vivado Design Timing Summary and utilization reports.

One generator, twenty configurations

5G NR specifies two base graphs and 51 lifting sizes. Because our decoder is emitted by a parameterized generator, we regenerated and re-implemented 20 distinct configurations end to end:

Fair-comparison note: the commercial IP is a runtime-flexible multi-standard core; our cores are per-configuration specialized netlists, which is precisely what the generator makes economical. Throughput depends on iteration count: figures with early termination are stated at the operating SNR; fixed-iteration apples-to-apples figures are available in the datasheet on request.

Deep-space links get one chance at a frame: there is no retransmission across an interplanetary distance, so the decoder has to be right the first time and it has to keep running. The build below is our scalar configuration, generated end to end by our own algorithm-to-silicon framework from the published CCSDS AR4JA code definitions. It processes one channel sample per clock, which keeps the datapath small and every stage auditable, and it is checked bit for bit against an independent software reference decoder written from the same published parity-check matrices. It trades throughput for that simplicity, so it is slower than the folded configuration we ship for rate-critical links. It is also the one we took all the way to a board, so it is the one whose numbers we publish.

Latency, per code point

Measured by interface lockstep at a fixed 8 iterations: the first output bit lands at an exactly predicted cycle for every configuration. These are the scalar configuration's figures. The folded product configuration processes several lanes per cycle and is correspondingly faster; ask us for figures on your target part rather than scaling these.

Fixed 8 iterations, no early termination, so these are worst-case figures rather than best-case ones. Early termination on the syndrome check is available and reduces the average iteration count at operating SNR. This configuration closed timing at its 208.3 MHz constraint on a ZCU102 (xczu9eg) with WNS +0.091 ns post-route; we are not publishing a clock for the RFSoC part, because the builds we have on that part do not meet that constraint. Device clock and resource figures for the folded product configuration on your target part are produced per configuration on request. We publish only numbers we have measured, on the part we measured them on.

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Real recorded data from the board: every frame, every configuration, the bit-error comparison and the BER waterfall. No hardware needed.

The CCSDS decoder is available as a SystemVerilog source licence. You receive the readable, editable RTL, the self-checking testbench that produced the numbers above, the reference vectors, a software reference model, and the datasheet and user guide in English and Chinese. There is no evaluation timeout and no device lock in this delivery.

Every row in this table comes from the same place-and-route run, so the clock and the resource figures describe one build rather than a best case assembled from several. Figures for your own target part are produced on request.

Request the datasheet Request the source licence

The datasheet and user guide are released to registered recipients. Tell us your name, company and work email and we will send both, in English or Chinese. Encrypted RTL, netlist and device-locked deliveries are also available when the source must not be readable.