LDPC Decoder IP: 5G NR, Wi-Fi, CCSDS

5G NR

Current NR product scope

The entry-level line offers runtime code selection with P64 encoding and P64/P128 decoding. These are candidate implementations with unsettled routed probes and pending package release. Their current specifications and qualified comparisons are on the dedicated product page.

Earlier specialized-core clock and throughput comparisons are not specifications for these runtime candidates. They have been removed from this sales page pending a separate evidence review. The existing hosted NR lab uses another implementation.

Review current encoder and decoder specifications Explore the existing hosted lab

SILICON

CCSDS AR4JA, proven on a deployed board

Deep-space links get one chance at a frame: there is no retransmission across an interplanetary distance, so the decoder has to be right the first time and it has to keep running. The build below is our scalar configuration, generated end to end by our own algorithm-to-silicon framework from the published CCSDS AR4JA code definitions. It processes one channel sample per clock, which keeps the datapath small and every stage auditable, and it is checked bit for bit against an independent software reference decoder written from the same published parity-check matrices. It trades throughput for that simplicity, so it is slower than the folded configuration we ship for rate-critical links. It is also the one we took all the way to a board, so it is the one whose numbers we publish.

9 / 9

Code points of CCSDS 131.0-B-3 covered by the scalar configuration MEASURED

675

Frames decoded on the board with 0 bit mismatches vs the reference model MEASURED

81 / 81

Reproducibility gate: 3 fresh boots × 9 configs × 3 trials, zero failures MEASURED

775 / 775

Frames bit-exact in simulation before silicon, all 9 configs MEASURED

Latency, per code point

Measured by interface lockstep at a fixed 8 iterations: the first output bit lands at an exactly predicted cycle for every configuration. These are the scalar configuration's figures. The folded product configuration processes several lanes per cycle and is correspondingly faster; ask us for figures on your target part rather than scaling these.

Configuration	Transmitted bits	Cycles / iteration	Frame latency (cycles)	Cycles / info bit
k = 1024, rate 1/2	2048	252	5,097	4.98
k = 1024, rate 2/3	1536	316	5,097	4.98
k = 1024, rate 4/5	1280	444	5,865	5.73
k = 4096, rate 1/2	8192	1240	22,217	5.42
k = 4096, rate 2/3	6144	844	17,001	4.15
k = 4096, rate 4/5	5120	444	12,777	3.12
k = 16384, rate 1/2	32768	4960	88,841	5.42
k = 16384, rate 2/3	24576	3376	67,977	4.15
k = 16384, rate 4/5	20480	2584	57,545	3.51

Fixed 8 iterations, no early termination, so these are worst-case figures rather than best-case ones. Early termination on the syndrome check is available and reduces the average iteration count at operating SNR. This configuration closed timing at its 208.3 MHz constraint on a ZCU102 (xczu9eg) with WNS +0.091 ns post-route; we are not publishing a clock for the RFSoC part, because the builds we have on that part do not meet that constraint. Device clock and resource figures for the folded product configuration on your target part are produced per configuration on request. We publish only numbers we have measured, on the part we measured them on.

Replay the silicon capture in your browser

Real recorded data from the board: every frame, every configuration, the bit-error comparison and the BER waterfall. No hardware needed.

LICENCE

CCSDS AR4JA source licence

Request a SystemVerilog source licence for the CCSDS decoder. The proposed package includes the readable, editable RTL, the self-checking testbench that produced the numbers above, the reference vectors, a software reference model, and the datasheet and user guide in English and Chinese. There is no evaluation timeout and no device lock in this delivery.

The exact configuration, current package release and licence terms are confirmed before payment.

Decoder architecture: channel LLR in at one sample per clock, message and a-posteriori stores in on-chip block RAM feeding a layered min-sum iteration engine, iteration and layer control with block length and rate latched per frame, decoded bits out at one bit per clock, and below it the deployed path from host through a data mover to the decoder core — Inside the core, and how it sits in a system. The block length and code rate are latched per frame, so one instance covers all nine code points without a rebuild.

£600

SystemVerilog source licence, one-off. Chinese page quotes ¥6,000

36 / 36

Frames the shipped package decodes bit-exact in Verilator and Vivado xsim, unmodified MEASURED

SystemVerilog modules, plus the schedule ROMs, and 0 encrypted or black-box files

What you receive	Detail
Synthesizable RTL	11 SystemVerilog modules and the schedule ROM contents, full plaintext
Self-checking testbench	Runs under Verilator or Vivado xsim from the shipped scripts, 9 configurations, 18 reference vector files
Software reference	MATLAB reference decoder and the published CCSDS parity-check matrices, for software against hardware comparison
Documentation	Datasheet and user guide, English and Chinese, with ports, parameters, protocol and resource figures
Integration example	Instantiation template and a constraints note
Customer-facing top	`ccsds_ldpc_top`, one core for all nine code points, selected per frame at runtime

Implemented figures, ZCU102 (xczu9eg-2)	Value
Clock closed, post-route	208.3 MHz, WNS +0.091 ns MEASURED
CLB LUTs	24,535 of 274,080, 8.95 % MEASURED
Registers	15,861 of 548,160, 2.89 % MEASURED
Block RAM tiles	225.5 of 912, 24.7 % MEASURED
DSP slices	0 MEASURED

Every row in this table comes from the same place-and-route run, so the clock and the resource figures describe one build rather than a best case assembled from several. Figures for your own target part are produced on request.

Replay of the recorded on-board capture: 421 frames through silicon, 802.8 thousand bits compared against the reference model, zero bit mismatches, and the per-configuration verdict grid — The recorded on-board capture, replayed frame by frame. Every number on it comes from the board, compared against the reference model on the host.

Request the datasheet Request the source licence

The datasheet and user guide are released to registered recipients. Tell us your name, company and work email and we will send both, in English or Chinese. Encrypted RTL, netlist and device-locked deliveries are also available when the source must not be readable.

CATALOG

Family members

5G NR (3GPP TS 38.212)

Runtime BG1 / BG2 · P64 / P128

Entry-level encoder and decoder candidates with configuration-specific routed-probe and model evidence. Release is pending; the hosted lab uses a separate implementation.

Review the current specifications

CCSDS AR4JA

Deep space · satellite

All nine AR4JA code points of CCSDS 131.0-B-3: block lengths 1024, 4096 and 16384 information bits, each at rate 1/2, 2/3 and 4/5. The folded configuration trades parallelism against area for rate-critical or power-constrained platforms; the scalar configuration is the build we verified bit-exact on real silicon, across all nine.

Frames decoded on silicon675, 0 bit errors MEASURED

Reproducibility gate81 / 81 runs MEASURED

Read the silicon case study

IEEE 802.11n

Wi-Fi · streaming

Continuously streaming decoder accepting one codeword after another with no inter-frame gap. The architectural template behind the whole family.

Clock (Virtex-7)312 MHz MEASURED

Initiation intervalII = 1

Need a different standard, rate, or block size? New configurations are generated and re-verified in days: see IP customization.

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