Bring an algorithm, an existing RTL design, or a board integration problem. We agree on the target, workload, deliverables, and acceptance checks before work begins.
You provide an executable reference, target device, constraints, and representative data. The scoped delivery can include an architecture record, synthesizable RTL, comparison tests, and implementation reports.
Capture behavior, precision, interfaces, target hardware, and acceptance criteria.
Develop the hardware architecture and compare models and RTL against an independent reference.
Run the agreed tool flow and provide source, tests, reports, and integration notes.
Teams that want to use the software directly can evaluate Python2Verilog.
For RTL that does not meet a clock target, we measure the failing paths, identify the limiting mechanism, test a structural change, and rerun functional and implementation checks. The deliverable includes the before-and-after reports on the same target and constraints.
Read a device-specific closure case studyWe adapt a catalog core to an agreed code rate, block length, channel count, bit width, or device. The scope includes the new configuration, comparison tests, and implementation evidence appropriate to the target.
For existing RTL, we define an independent reference and test plan, then check the stated behaviors at bit, cycle, and interface boundaries. Real-data replay and stress cases are selected for the project.
We integrate agreed FPGA functions with board interfaces, embedded software, host processing, and application tests. The handover includes build instructions and a board acceptance record when hardware is in scope. See the RFSoC WLAN case study for a specific deployed example.