AlgoSilicon Ltd develops the Python2Verilog platform, licenses FPGA IP cores, and undertakes engineering projects that connect algorithms to working hardware.
Customers can evaluate Python2Verilog on a defined algorithm, license an existing IP core, or commission design and system-integration work. Current public examples include WLAN receive systems and LDPC decoding on specific FPGA platforms. Other application areas are evaluated against each customer's target and acceptance criteria.
AlgoSilicon was founded by Dr. Jie Lei, a signal-processing and communications engineer with a PhD in the field and more than twenty years building hardware for wireless, satellite, and space systems.
State the target, workload, interfaces, and acceptance checks before using a result.
Attach test and implementation reports to the build they assess; label design targets separately.
When deployment is in scope, verify the agreed function on the named board and record limits.